1. Field of the Invention
This invention relates to frequency synthesis and division and more particularly to a digital variable clock divider circuit which uses phase slip techniques to provide a wider range of available output frequencies from a given input frequency.
2. Description of Related Art
Frequency dividers are well known in the digital arts to provide a selectable variety of output clock waveform frequencies from a single input clock waveform signal. Such devices are useful in the digital electronic arts to provide a variety of output clock signals at various frequencies for use by components of an electronic circuit. For example, a processor (CPU) device in an electronic application may use a different frequency clock waveform than associated memory devices. Likewise, attached peripheral I/O controller devices may require still other clock signal frequencies. Rather than provide a plurality of discrete frequency generating oscillators on such an application circuit, simpler, less costly, frequency divider devices are applied to generate one or more additional frequencies from a single input signal waveform. Each frequency divider circuit can produce a particular frequency by xe2x80x9cdividingxe2x80x9d the input signal waveform to produce a desired output signal waveform having the desired frequency.
As taught by prior techniques, many frequency divider circuits are capable of producing only integral multiples of the applied input frequency. In other words, the output frequency from frequency dividers as previously taught in the art can produce output waveforms having the input waveform frequency divided by 2, 3, 4, etc.
Frequency divider circuits are often applied for clock timing used in a memory controller. The memory controller controls a wide variety of timing parameters in the associated memory devices and therefore requires high granularity from the derived frequencies. Mere integer division of the input frequency does not provide sufficient granularity of the generated (synthesized) clock signals.
Other known frequency divider designs are capable of producing output frequencies through division by integer and non-integer values. Some such circuit designs, for example, use a frequency synthesizer to multiply the input clock by an integer N and then perform an integral division of that resultant clock by an integer M. The resultant clock is therefore an N/M division of the input clock. However, the particular selections of M and N are fixed by the standard integer division circuits used. In addition, such designs require the addition of a frequency synthesizer analog component. Such devices are not only relatively complex, but such analog components tend to introduce problems relating to circuit packaging and power dissipation as compared to digital circuits.
Another simple technique for achieving non-integer division of a clock signal which avoids use of complex analog components is one which uses both the rising and falling edge of the input clock signal to derive a frequency which is an integer division of twice the input frequency. This simple technique, though simpler than the above noted frequency synthesizer approach, is limited in the flexibility of non-integral division capability. Only divisions of twice the input frequency may be generated.
In view of the above it is clear that a need exists to derive an output waveform from an input waveform with a simple circuit capable of producing integer as well as non-integer divisions of the input waveform frequency. In addition, a need exists for such a circuit to produce a wide variety of integer and non-integer divisions of the input waveform frequency to thereby increase the granularity of frequency selections for the derived output waveform frequency. Lastly, there is a need for such a circuit to be simple using digital logic as distinct from analog components.
This present invention solves the above and other problems, thereby advancing the useful arts, by providing an electronic circuit and associated method of operation to synthesize a desired output clock waveform from multiphase input clock waveforms using combinations of integer and non-integer divisions of the input clocks available for generation of the output clock. In addition, the circuits of the present invention generate the desired clocks using exclusively digital logic devices thereby avoiding problems known in the use of analog frequency synthesizers, and other analog circuits. The circuit of the present invention includes a first portion for performing well known integral division of the input clock waveforms in combination with a second portion for phase slip control to perform non-integer division of the source input waveform. A control portion of the circuit multiplexes and integrates the operation of the other two portions to thereby produce a desired output waveform as a divided transformation of the source input clock.
The source input signal is provided by a multi-phase frequency synthesizer producing a plurality of phases of a fixed frequency clock. The plurality of phases supplied are preferably at fixed and equal relative phase offsets. The period of the output signal of the digital divider circuit of the present invention is a multiple of its input signal period plus or minus a multiple of the minimal phase shift provided by the phase portion of the circuit. The phase control portion of the circuit includes a plurality of single phase slip circuits each associated with one of the multiple source input phases for control of the combination of the multiple input phases to produce the desired waveform. A standard integral divider circuit in each single phase slip circuit first performs a desired integral division on the source input clock. This intermediate output clock signal is then applied to the phase slip portion of the single phase slip circuit for generation of the final desired output clock waveform.
For example, if the frequency synthesizer portion of the present invention has four evenly spaced output phases, then the period of the output signal waveform of the digital clock divider of the present invention can be the input period times 1.00, 1.25, 1.50, 1.75, 2.00, 2.25, etc. Thus, the simple addition of more synthesizer phases in the frequency synthesizer portion (and associated single phase slip circuits) provides higher granularity options for the output signal waveform frequency.
In a first embodiment of the present invention, an input clock waveform signal is first divided by an integral divisor. The result of the integer division is then applied to the phase slip portion of the circuit to generate the desired output waveform. In a second embodiment of the present invention, the input signal waveform is first applied to the phase shift portion of the circuit. The result of the phase shift is then applied to a standard integer clock divider to generate the desired output signal waveform. The first embodiment is capable of generating a wider variety of output waveforms than is the second embodiment. However, the second embodiment is simpler and therefore less costly in particular applications. The preferred or best presently known mode as between these two options depends upon the particular requirements of a particular application.
In the first embodiment, a frequency synthesizer portion generates multiple phase shifted output waveforms from an input waveform signal. The predetermined phases of the waveform are applied to the divider circuit of the present invention, one phase output applied to a unique one of a plurality of single phase slip dividers. A ripple shift register is used to align the multiple phases applied to the divider portion of the present invention. Each phase aligned waveform synchronously clocks one of a plurality of single phase slip divider circuits to produce an output clock phase aligned to this synthesizer phase. Each single phase slip divider circuit also synchronously determines when its generated output should be applied to the output of the divider by providing a first level multiplexing of the final output phase signal. A shift register within each single phase slip divider controls the multiplexing of the output signal of each single phase slip divider for application to the out signal path of the divider.
More specifically, each frequency synthesizer phase output is divided by an integer value to produce the base period applied to each of the plurality of single phase slip dividers. Each single phase slip divider circuit determines when its output clock phase should become the output clock for the digital divider. This determination is controlled by a shift register in each single phase slip divider which shifts on each base divide. For example, phase 0 could cause the final output to become high first, then phase 1 could cause the final output to become high, then phases 2, 3, 4, 5, etc. in turn. This results in a waveform where the next active pulse is slipped by the difference between phases. The base divide (integral divide) and the number of phases to slip each time is programmable such that the resulting period can be programmed to any multiple of the basic phase shift delta.
In the second embodiment of the present invention, a phase slip circuit can optionally switch to the earlier phase of the frequency synthesizer outputs at each clock edge. This embodiment of the divider circuit of the present invention, while simpler and thereby less costly, allows a maximum frequency which is (nxe2x88x921)/n of the frequency synthesizer""s base frequency (where n is the number of phases generated by the multi-phase frequency synthesizer). This circuit can optionally remain on the same phase output at each clock edge to thereby allow the resultant output waveform frequency to be varied. A separate ring counter of variable length indicates when to shift to the next phase or stay on the same phase (non-shifts). As above in the first embodiment, a standard integral divider circuit is used to further reduce the output frequency toward the desired frequency. Since each period of the standard integral divider output waveform must be the same (to repeat the desired waveform), the number of shifts and non-shifts in the phase slip circuit must be the same during each period of the integral divider output waveform.
It is therefore an object of the present invention to provide a clock divider circuit and associated methods of operation which provides integral and non-integral clock division.
It is a further object of the present invention to provide a clock divider circuit and associated methods of operation which provides integral and non-integral clock division with improved granularity of non-integral clock division.
It is still a further object of the present invention to provide a clock divider circuit and associated methods of operation which combine an integral division of a clock with a variable phase slip for non-integral clock division.
It is another object of the present invention to provide a clock divider circuit and associated methods of operation which first performs phase slip for non-integral clock division followed by integral clock division.
It is still another object of the present invention to provide a clock divider circuit and associated methods of operation which first performs integral clock division followed by phase slip for non-integral clock division.
It is yet another object of the invention to provide a clock divider circuit and associated methods of operation which perform integral and non-integral clock division using digital logic devices substantially devoid of analog components.